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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual Precision Monostable Multivibrator (Retriggerable, Resettable)
The MC54/74HC4538A is identical in pinout to the MC14538B. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This dual monostable multivibrator may be triggered by either the positive or the negative edge of an input pulse, and produces a precision output pulse over a wide range of pulse widths. Because the device has conditioned trigger inputs, there are no trigger-input rise and fall time restrictions. The output pulse width is determined by the external timing components, Rx and Cx. The device has a reset function which forces the Q output low and the Q output high, regardless of the state of the output pulse circuitry. * Unlimited Rise and Fall Times Allowed on the Trigger Inputs * Output Pulse is Independent of the Trigger Pulse Width * 10% Guaranteed Pulse Width Variation from Part to Part (Using the Same Test Jig) * Output Drive Capability: 10 LSTTL Loads * Outputs Directly Interface to CMOS, NMOS and TTL * Operating Voltage Range: 3.0 to 6.0 V * Low Input Current: 1.0 A * High Noise Immunity Characteristic of CMOS Devices * In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 145 FETs or 36 Equivalent Gates
MC54/74HC4538A
16 1
J SUFFIX CERAMIC PACKAGE CASE 620-10
16 1
N SUFFIX PLASTIC PACKAGE CASE 648-08
16 1
D SUFFIX SOIC PACKAGE CASE 751B-05 ORDERING INFORMATION
MC54HCXXXXAJ MC74HCXXXXAN MC74HCXXXXAD
Ceramic Plastic SOIC
PIN ASSIGNMENT
GND CX1/RX1 RESET 1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC GND CX2/RX2 RESET 2 A2 B2 Q2 Q2
LOGIC DIAGRAM
CX1 1 4 TRIGGER A1 INPUTS B1 5 3 15 TRIGGER INPUTS A2 B2 12 11 14 10 9 Reset Q2 Q2 H H H H H H L 2 6 7 Q1 Q1 CX2 RX2 VCC RX1 VCC
A1 B1 Q1 Q1 GND
FUNCTION TABLE
Inputs A L X H L,H, L X X L X H L,H, X X Not Triggered Not Triggered Not Triggered Not Triggered L H Not Triggered B H Outputs Q Q
RESET 1
RESET 2
13
PIN 16 = VCC PIN 8 = GND RX AND CX ARE EXTERNAL COMPONENTS PIN 1 AND PIN 15 MUST BE HARD WIRED TO GND
10/95
(c) Motorola, Inc. 1995
3-1
REV 6
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MC54/74HC4538A
MAXIMUM RATINGS*
Symbol VCC Vin Parameter Value Unit V V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) - 0.5 to + 7.0 - 1.5 to VCC + 1.5 - 0.5 to VCC + 0.5 20 30 25 50 750 500 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin A, B, Reset Cx, Rx mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package Storage Temperature mW Tstg TL - 65 to + 150 260 300
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
v
v
_C _C
Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) (Ceramic DIP)
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C Ceramic DIP: - 10 mW/_C from 100_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol VCC
Parameter
Min
Max 6.0
Unit V V
DC Supply Voltage (Referenced to GND)
3.0** 0
Vin, Vout TA
DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 7) A or B (Figure 5)
VCC
- 55 0 0 0
+ 125 1000 500 400
_C
ns
tr, tf
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
--
No Limit * * *
Rx Cx
External Timing Resistor
VCC < 4.5 V VCC 4.5 V
1.0 2.0 0
k F
External Timing Capacitor
* The maximum allowable values of Rx and Cx are a function of the leakage of capacitor Cx, the leakage of the HC4538A, and leakage due to board layout and surface resistance. For most applications, Cx/Rx should be limited to a maximum value of 10 F/1.0 M. Values of Cx > 1.0 F may cause a problem during power down (see Power Down Considerations). Susceptibility to externally induced noise signals may occur for Rx > 1.0 M. ** The HC4538A will function at 2.0 V but for optimum pulse width stability, VCC should be above 3.0 V. NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
MOTOROLA
3-2
High-Speed CMOS Logic Data DL129 -- Rev 6
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DC CHARACTERISTICS FOR THE MC54/74HC4538A
Symbol VOH VOL ICC ICC VIH VIL Iin Iin Maximum Supply Current (per package) Active State Maximum Quiescent Supply Current (per package) Standby State Maximum Input Leakage Current (Rx, Cx) Maximum Input Leakage Current (A, B, Reset) Maximum Low-Level Output Voltage Minimum High-Level Output Voltage Maximum Low-Level Input Voltage Minimum High-Level Input Voltage Parameter Vin = VIH or VIL |Iout| 4.0 mA |Iout| 5.2 mA Vin = VIH or VIL |Iout| 20 A Vin = VIH or VIL |Iout| - 4.0 mA |Iout| - 5.2 mA Vin = VIH or VIL |Iout| 20 A Vin = VCC or GND Q1 and Q2 = High Iout = 0 A Pins 2 and 14 = 0.5 VCC Vin = VCC or GND Q1 and Q2 = Low Iout = 0 A Vin = VCC or GND Vin = VCC or GND Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
High-Speed CMOS Logic Data DL129 -- Rev 6
v v
v
v v
v
v
v
Test Conditions
3-3 VCC Volts 6.0 6.0 6.0 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 1.5 3.15 4.2 3.98 5.48 Min 1.9 4.4 5.9 - 55 to 25_C 25_C 0.1 0.5 1.35 1.8 0.26 0.26 Max 50 400 130 0.1 0.1 0.1 Guaranteed Limits 1.5 3.15 4.2 3.84 5.34 Min 1.9 4.4 5.9 - 45_C to 85_C
v 85_C
500
1.0
0.5 1.35 1.8
0.33 0.33
Max
600
220
0.1 0.1 0.1
MC54/74HC4538A
1.5 3.15 4.2
Min
3.7 5.2
1.9 4.4 5.9
- 55_C to 125_C
v 125_C
500
1.0
0.5 1.35 1.8
Max
800
350
0.4 0.4
0.1 0.1 0.1
MOTOROLA Unit A A A nA V V V V
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I III I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I IIII I I I I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I IIII I I I I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII III IIIIIIIIIIIIIIIIIIIIII IIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II III III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I III I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
* Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High- Speed CMOS Data Book (DL129/D).
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AC CHARACTERISTICS FOR THE MC54/74HC4538A (CL = 50 pF, Input tr = tf = 6.0 ns)
MOTOROLA
TIMING CHARACTERISTICS FOR THE MC54/74HC4538A (Input tr = tf = 6.0 ns)
MC54/74HC4538A
Symbol
Symbol
tPLH
tPHL
tPHL
tPLH
tTLH tTHL
CPD
tr, tf
trec
Cin
tw
tw
Power Dissipation Capacitance (Per Multivibrator)*
A or B (Figure 7)
Maximum Input Rise and Fall Times, Reset (Figure 7)
Minimum Pulse Width, Reset (Figure 7)
Minimum Pulse Width, Input A or B (Figure 6)
Minimum Recovery Time, Inactive to A or B (Figure 7)
Maximum Input Capacitance
Maximum Output Transition Time, Any Output (Figures 7 and 8)
Maximum Propagation Delay Reset to NQ (Figures 7 and 8)
Maximum Propagation Delay Reset to Q (Figures 7 and 8)
Maximum Propagation Delay Input A or B to NQ (Figures 6 and 8)
Maximum Propagation Delay Input A or B to Q (Figures 6 and 8)
Parameter
Parameter
(A. B, Reset) (Cx, Rx)
3-4 VCC Volts VCC Volts 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 -- Min Min 60 12 10 60 12 10 0 0 0 - 55 to 25_C - 55 to 25_C 1000 500 400 Max Max 175 35 30 175 35 30 195 39 33 175 35 30 10 25 75 15 13 Min Min 75 15 13 75 15 13 0 0 0 150
Typical @ 25C, VCC = 5.0 V
Guaranteed Limits
Guaranteed Limits
No Limit
v 85_C
v 85_C
1000 500 400
Max
Max
220 44 37
220 44 37
245 49 42
220 44 37
High-Speed CMOS Logic Data DL129 -- Rev 6 10 25 95 19 16 Min Min 90 18 15 90 18 15 0 0 0
v 125_C
v 125_C
1000 500 400 Max Max 110 22 19 265 53 45 265 53 45 295 59 50 265 53 45 10 25
Unit
Unit
pF
pF
ns ns ns ns ns ns ns ns ns
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I III I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
* For output pulse widths greater than 100 s, typically = kRxCx, where the value of k may be found in Figure 1.
High-Speed CMOS Logic Data DL129 -- Rev 6
OUTPUT PULSE WIDTH CHARACTERISTICS (CL = 50 pF)t
Symbol
0.3
k, OUTPUT PULSE WIDTH CONSTANT (TYPICAL)
0.4
0.7
OUTPUT PULSE WIDTH ( )
0.5
0.6
0.8
--
--
Figure 1. Typical Output Pulse Width Constant, k, versus Supply Voltage (For output pulse widths > 100 s: = kRxCx)
1
Pulse Width Match Variation (Part to Part)
Pulse Width Match Between Circuits in the same Package
Output Pulse Width* (Figures 6 and 8)
2
3 4 5 6 VCC, POWER SUPPLY VOLTAGE (VOLTS)
Parameter
0.5
0.6
OUTPUT PULSE WIDTH (t) (NORMALIZED TO 5 V NUMBER)
0.7
0.8
0.9
1.1
1
1
Rx = 10 k, Cx = 0.1 F
Timing Components
Rx = 100 k Cx = 1000 pF
TA = 25C
Figure 3. Normalized Output Pulse Width versus Power Supply Voltage
2
Conditions
3 4 5 6 VCC, POWER SUPPLY VOLTAGE (VOLTS)
--
--
Rx = 1 M Cx = 0.1 F
7
3-5 100 ms 100 s 1 k 100 ns 0.00001 0.0001 10 ms 10 s 100 k VCC Volts 1 ms 1 s 10 s 5.0 -- -- 1s 10 k 1 M VCC = 5 V, TA = 25C 0.63 Min - 55 to 25_C TA = 25C 0.77 Max 0.001 Guaranteed Limits Min 0.6 0.01 0.1 CAPACITANCE (F) 7
Figure 2. Output Pulse Width versus Timing Capacitance
v 85_C
5.0
10
Max
0.8
MC54/74HC4538A
0.59
Min
v 125_C
1
0.81
Max
MOTOROLA 10 Unit ms % % 100
MC54/74HC4538A
1.1 OUTPUT PULSE WIDTH ( ) (NORMALIZED TO 25 C NUMBER) 1.05 1 0.95 0.9 0.85 VCC = 3 V 0.8 - 75 - 50 - 25 0 25 50 75 100 125 150 VCC = 6 V Rx = 10 k Cx = 0.1 F
TA, AMBIENT TEMPERATURE (C)
Figure 4. Normalized Output Pulse Width versus Power Supply Voltage
1.03 OUTPUT PULSE WIDTH ( ) (NORMALIZED TO 25 C NUMBER) 1.02 1.01 1 0.99 0.98 VCC = 4.5 V 0.97 - 75 - 50 - 25 0 25 50 75 100 125 150 VCC = 5.5 V VCC = 5 V Rx = 10 k Cx = 0.1 F
TA, AMBIENT TEMPERATURE (C)
Figure 5. Normalized Output Pulse Width versus Power Supply Voltage
MOTOROLA
3-6
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HC4538A
SWITCHING WAVEFORMS
tw(H) VCC 50% A tw(L) B 50% VCC GND tPLH 50% Q tPHL Q 50% tPHL tPLH GND
tr 90% A 10%
tf
Figure 6.
VCC GND trr VCC 50%
B tf RESET tTLH 90% Q tTHL Q 90% 10% 10% tPLH 50% 50% tw(L) tPHL 50% 50% tf 90% 10% trec + trr (RETRIGGERED PULSE)
GND
VCC GND
Figure 7.
TEST POINT OUTPUT DEVICE UNDER TEST CL*
* Includes all probe and jig capacitance
Figure 8. Test Circuit
High-Speed CMOS Logic Data DL129 -- Rev 6
3-7
MOTOROLA
MC54/74HC4538A
PIN DESCRIPTIONS
INPUTS A1, A2 (Pins 4, 12) Positive-edge trigger inputs. A rising-edge signal on either of these pins triggers the corresponding multivibrator when there is a high level on the B1 or B2 input. B1, B2 (Pins 5, 11) Negative-edge trigger inputs. A falling-edge signal on either of these pins triggers the corresponding multivibrator when there is a low level on the A1 or A2 input. Reset 1, Reset 2 (Pins 3, 13) Reset inputs (active low). When a low level is applied to one of these pins, the Q output of the corresponding multivibrator is reset to a low level and the Q output is set to a high level. CX1/RX1 and CX2/RX2 (Pins 2 and 14) External timing components. These pins are tied to the common points of the external timing resistors and capacitors (see the Block Diagram). Polystyrene capacitors are recommended for optimum pulse width control. Electrolytic capacitors are not recommended due to high leakages associated with these type capacitors. GND (Pins 1 and 15) External ground. The external timing capacitors discharge to ground through these pins. OUTPUTS Q1, Q2 (Pins 6, 10) Noninverted monostable outputs. These pins (normally low) pulse high when the multivibrator is triggered at either the A or the B input. The width of the pulse is determined by the external timing components, RX and CX. Q1, Q2 (Pins 7, 9) Inverted monostable outputs. These pins (normally high) pulse low when the multivibrator is triggered at either the A or the B input. These outputs are the inverse of Q1 and Q2.
LOGIC DETAIL (1/2 THE DEVICE)
RxCx UPPER REFERENCE CIRCUIT - + Vre, UPPER LOWER REFERENCE CIRCUIT - + Vre, LOWER Q
OUTPUT LATCH
VCC
VCC M2
M1 2 k
M3
Q
TRIGGER CONTROL CIRCUIT A C CB R Q TRIGGER CONTROL RESET CIRCUIT
B
RESET
POWER ON RESET RESET LATCH
Figure 9.
MOTOROLA
3-8
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HC4538A
CIRCUIT OPERATION
Figure 12 shows the HC4538A configured in the retriggerable mode. Briefly, the device operates as follows (refer to Figure 10): In the quiescent state, the external timing capacitor, Cx, is charged to V CC. When a trigger occurs, the Q output goes high and C x discharges quickly to the lower reference voltage (Vref Lower 1/3 V CC). Cx then charges, through Rx, back up to the upper reference voltage (Vref Upper 2/3 V CC), at which point the one-shot has timed out and the Q output goes low. The following, more detailed description of the circuit operation refers to both the logic detail (Figure 9) and the timing diagram (Figure 10). TRIGGER OPERATION The HC4538A is triggered by either a rising-edge signal at input A (#7) or a falling-edge signal at input B (#8), with the unused trigger input and the Reset input held at the voltage levels shown in the Function Table. Either trigger signal will cause the output of the trigger-control circuit to go high (#9). The trigger-control circuit going high simultaneously initiates two events. First, the output latch goes low, thus taking the Q output of the HC4538A to a high state (#10). Second, transistor M3 is turned on, which allows the external timing capacitor, Cx, to rapidly discharge toward ground (#11). (Note that the voltage across Cx appears at the input of both the upper and lower reference circuit comparator). When Cx discharges to the reference voltage of the lower reference circuit (#12), the outputs of both reference circuits will be high (#13). The trigger-control reset circuit goes high, resetting the trigger-control circuit flip-flop to a low state (#14). This turns transistor M3 off again, allowing Cx to begin to charge back up toward VCC, with a time constant t = RxCx (#15). Once the voltage across Cx charges to above the lower reference voltage, the lower reference circuit will go low allowing the monostable multivibrator to be retriggered.
TRIGGER CYCLE (B INPUT)
[
[
QUIESCENT STATE In the quiescent state, before an input trigger appears, the output latch is high and the reset latch is high (#1 in Figure 10). Thus the Q output (pin 6 or 10) of the monostable multivibrator is low (#2, Figure 10). The output of the trigger-control circuit is low (#3), and transistors M1, M2, and M3 are turned off. The external timing capacitor, Cx, is charged to VCC (#4), and both the upper and lower reference circuit has a low output (#5). In addition, the output of the trigger-control reset circuit is low.
QUIESCENT STATE TRIGGER CYCLE (A INPUT)
RESET
RETRIGGER
7
trr
TRIGGER INPUT A (PIN 4 OR 12) TRIGGER INPUT B (PIN 5 OR 11)
9
8 24
TRIGGER-CONTROL CIRCUIT OUTPUT RX/CX INPUT (PIN 2 OR 14)
3 4 12 13 11
14 21 23
15
17
Vref LOWER 5 UPPER REFERENCE CIRCUIT LOWER REFERENCE CIRCUIT RESET INPUT (PIN 3 OR 13)
1 6
Vref UPPER
18
25
13 16
20
RESET LATCH
10
22
Q OUTPUT (PIN 6 OR 10)
2
19
+ trr
Figure 10. Timing Diagram
High-Speed CMOS Logic Data DL129 -- Rev 6
3-9
MOTOROLA
MC54/74HC4538A
When Cx charges up to the reference voltage of the upper reference circuit (#17), the output of the upper reference circuit goes low (#18). This causes the output latch to toggle, taking the Q output of the HC4538A to a low state (#19), and completing the time-out cycle. POWER-DOWN CONSIDERATIONS Large values of Cx may cause problems when powering down the HC4538A because of the amount of energy stored in the capacitor. When a system containing this device is powered down, the capacitor may discharge from V CC through the input protection diodes at pin 2 or pin 14. Current through the protection diodes must be limited to 30 mA; therefore, the turn-off time of the VCC power supply must not be faster than t = V C C C x / (30 mA). For example, if V CC = 5.0 V and Cx = 15 F, the VCC supply must turn off no faster than t = (5.0 V)(15 F)/30 mA = 2.5 ms. This is usually not a problem because power supplies are heavily filtered and cannot discharge at this rate. When a more rapid decrease of VCC to zero volts occurs, the HC4538A may sustain damage. To avoid this possibility, use an external damping diode, D x, connected as shown in Figure 11. Best results can be achieved if diode Dx is chosen to be a germanium or Schottky type diode able to withstand large current surges. RESET AND POWER ON RESET OPERATION A low voltage applied to the Reset pin always forces the Q output of the HC4538A to a low state. The timing diagram illustrates the case in which reset occurs (#20) while Cx is charging up toward the reference voltage of the upper reference circuit (#21). When a reset occurs, the output of the reset latch goes low (#22), turning on transistor M1. Thus Cx is allowed to quickly charge up to VCC (#23) to await the next trigger signal. On power up of the HC4538A the power-on reset circuit will be high causing a reset condition. This will prevent the trigger-control circuit from accepting a trigger input during this state. The HC4538A's Q outputs are low and the Q not outputs are high. RETRIGGER OPERATION When used in the retriggerable mode (Figure 12), the HC4538A may be retriggered during timing out of the output pulse at any time after the trigger-control circuit flip-flop has been reset (#24), and the voltage across Cx is above the lower reference voltage. As long as the Cx voltage is below the lower reference voltage, the reset of the flip-flop is high, disabling any trigger pulse. This prevents M3 from turning on during this period resulting in an output pulse width that is predictable. The amount of undershoot voltage on RxCx during the trigger mode is a function of loop delay, M3 conductivity, and V DD. Minimum retrigger time, trr (Figure 7), is a function of 1) time to discharge R x C x from V DD to lower reference voltage (T discharge); 2) loop delay (T delay); 3) time to charge R x C x from the undershoot voltage back to the lower reference voltage (Tcharge). Figure 13 shows the device configured in the non-retriggerable mode. An Application Note (AN1558/D) titled Characterization of Retrigger Time in the HC4538A Dual Precision Monstable Multivibrator is being prepared. Please consult the factory for its availability.
DX CX RX VCC
A B
Q Q
RESET
Figure 11. Discharge Protection During Power Down
MOTOROLA
3-10
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HC4538A
TYPICAL APPLICATIONS
CX RISING-EDGE TRIGGER A B B = VCC RESET = VCC RESET = VCC RX VCC Q Q RISING-EDGE TRIGGER A B Q CX RX VCC Q
CX
RX VCC Q
CX
RX VCC Q
A = GND
A B FALLING-EDGE TRIGGER Q
B FALLING-EDGE TRIGGER
Q
RESET = VCC
RESET = VCC
Figure 12. Retriggerable Monostable Circuitry
Figure 13. Non-retriggerable Monostable Circuitry
ONE-SHOT SELECTION GUIDE
100 ns MC14528B MC14536B MC14538B MC14541B HC4538A* 1 s 10 s 100 s 1 ms 10 ms 100 ms 1s 10 s 23 HR 5 MIN * Limited operating voltage (2 - 6 V) TOTAL OUTPUT PULSE WIDTH RANGE RECOMMENDED PULSE WIDTH RANGE
High-Speed CMOS Logic Data DL129 -- Rev 6
3-11
MOTOROLA
MC54/74HC4538A
OUTLINE DIMENSIONS
-A -
16 9
J SUFFIX CERAMIC PACKAGE CASE 620-10 ISSUE V
-B - C L
1
8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. INCHES MIN MAX 0.750 0.785 0.240 0.295 -- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 15 0 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 -- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 15 0 1.01 0.51
-T
SEATING - PLANE
N E F G D 16 PL 0.25 (0.010)
M
K M J 16 PL 0.25 (0.010)
M
TB
S
TA
S
DIM A B C D E F G J K L M N
-A -
16 9
N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R
B
1
8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 6.35 0.250 0.270 6.85 3.69 0.145 0.175 4.44 0.39 0.015 0.021 0.53 1.02 0.040 0.070 1.77 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.21 0.008 0.015 0.38 2.80 0.110 0.130 3.30 7.50 0.295 0.305 7.74 0 0 10 10 0.020 0.040 0.51 1.01
F S
C
L
-T - H G D 16 PL 0.25 (0.010)
M
SEATING PLANE
K
J TA
M
M
-A -
16 9
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
-B -
1 8
P 8 PL 0.25 (0.010)
M
B
M
G F
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019
K C -T SEATING -
PLANE
R X 45
M D 16 PL 0.25 (0.010)
M
J
T
B
S
A
S
MOTOROLA
3-12
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HC4538A
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High-Speed CMOS Logic Data DL129 -- Rev 6
CODELINE
*MC54/74HC4538A/D*
3-13
MC54/74HC4538A/D MOTOROLA

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